The ATtiny 10 is a low-power, CMOS 8-bit microcontroller based on the AVR-enhanced RISC architecture. The ATtiny 10 is a 6/8-pin device ranging from 512 Bytes to 1024 Bytes Flash, with 32 Bytes SRAM.
By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
UDFN Package
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SOT-23 Package
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Imagine a buzzing bee - small, nimble, and packed with power. Now, picture a similar powerhouse in the world of electronics, the ATtiny10 microcontroller. Developed by Atmel Corporation, the ATtiny10 is a part of the AVR family, distinguished by its low power consumption and high performance.
The ATtiny10 is more than just a microcontroller; it is the epitome of efficiency, capable of executing complex tasks despite its minimalistic design. Think of it as a virtuoso violinist capable of producing a symphony's worth of sound with just four strings!
Block Diagram
The AVR core combines a rich instruction set with 16 general-purpose working registers and system registers.
All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
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The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny 10 provides the following features -
- 512/1024 bytes of In-System Programmable Flash
- 32 bytes of SRAM
- four general-purpose I/O lines
- 16 general-purpose working registers
- 16-bit timer/counter with two PWM channels
- Internal and external interrupts
- A programmable watchdog timer with an internal oscillator
- An internal calibrated oscillator
- Four software selectable power saving modes
- ATtiny5/10 is also equipped with a four-channel, 8-bit Analog to Digital Converter (ADC).
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by
stopping the CPU and all I/O modules except the ADC.
In Power-down mode, registers keep their contents and all chip
functions are disabled until the next interrupt or hardware reset.
In Standby mode, the oscillator is running while the rest of
the device is sleeping, allowing a very fast start-up combined with low power consumption.
Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10
A comparison of the devices is shown in Table -
| Device |
Flash |
ADC |
Signature |
| ATtiny4 |
512 bytes |
No |
0x1E 0x8F 0x0A |
| ATtiny5 |
512 bytes |
Yes |
0x1E 0x8F 0x09 |
| ATtiny9 |
1024 bytes |
No |
0x1E 0x90 0x08 |
| ATtiny10 |
1024 bytes |
Yes |
0x1E 0x90 0x03 |
ATtiny10 Pinouts
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Pins Description -
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability.
As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running and provided the reset pin has not been disabled.