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ATmega8 USART

Serial Communication Interfaces

The concept of serial communication isn't new. As electronic devices grew in complexity, so did the need for them to communicate. The early days witnessed basic communication systems that laid the foundation for what we now know as USART.

USART came as a successor to simpler protocols, bringing the flexibility of synchronous and asynchronous operations. Over the years, as technology evolved, USART underwent improvements, adding features that made communication more reliable and faster.

Atmega8 usart block diagram

In the world of microcontrollers, the ability to communicate with external devices and interfaces is crucial. For Atmega8, a popular microcontroller from Atmel's AVR family, this communication capability is facilitated through USART (Universal Synchronous and Asynchronous Serial Receiver and Transmitter).

What is USART?

USART stands for Universal Synchronous and Asynchronous Serial Receiver and Transmitter. It's a hardware communication protocol that allows microcontrollers to communicate with other devices, such as computers, sensors, and other microcontrollers, either synchronously or asynchronously.

listAtmega8 USART Features

Full Duplex Operation

Enables simultaneous transmission and reception of data.

Configurable Baud Rate

Allows developers to set the speed of data transmission.

Frame Format Selection

Data can be sent in various frame formats, ensuring flexibility.

Parity Generation and Check

Ensures data integrity during transmission.

Multi-processor Communication Mode

Allows communication with multiple devices.

Modes of Operation

Atmega8's USART module is versatile, offering various modes of operation. The choice of mode is crucial, as it affects both data transmission and reception.

Asynchronous Mode

Here, there's no need for a shared clock signal between the transmitting and receiving devices. The data transmission relies on a pre-agreed baud rate. While it's easier to set up and less complex, there's a slight risk of data corruption if the baud rates mismatch.

Synchronous Mode

This mode uses a shared clock signal, synchronizing the transmitting and receiving devices. While it's more robust in terms of data integrity, the setup is slightly complex due to the need for a shared clock line.

Interrupts

Interrupts play a pivotal role, especially in USART communication. They facilitate non-polling, efficient operations.

  • USART_RX

    This interrupt is triggered when there's unread data in the receive buffer.

  • USART_UDRE

    Triggered when the transmit buffer is ready to receive new data.

  • USART_TX

    Occurs when the transmit buffer is empty, indicating that it's ready for the next byte.

Using these interrupts, Atmega8 USART communication becomes efficient, allowing the microcontroller to multitask effectively.

Error Handling

Errors are inevitable in any communication system. But what sets a system apart is how effectively it can detect and manage these errors.

  1. Framing Error (FE)

    Occurs when there's a mismatch between the number of stop bits..

  2. Data OverRun (DOR)

    Triggered when the receive buffer is full and the next byte has completely arrived..

  3. Parity Error (PE)

    Indicates a parity bit mismatch..

By effectively handling these errors, Atmega8 ensures robust USART communication.

USART vs. UART

While the terms are often used interchangeably, there are distinct differences:

UART (Universal Asynchronous Receiver Transmitter)

It exclusively deals with asynchronous operations. Without a clock, data transfer relies on predefined baud rates.

USART

It is the more advanced of the two, accommodating both synchronous (with clock) and asynchronous (without clock) operations. This dual nature makes USART suitable for a wider array of applications than UART.

ATmega8 USART Frame Format

The USART (Universal Synchronous and Asynchronous Receiver-Transmitter) module in the Atmega8 microcontroller facilitates serial communication, both synchronous and asynchronous. One of the critical aspects that make communication possible and accurate is the frame format used by USART.

ATmega8 Usart Frame Format

St

Start bit, always low

(n)

Data bits (0 to 8)

P

Parity bit. Can be odd or even

Sp

Stop bit, always high IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high

Structure of USART Frame Format

A USART frame in Atmega8 consists of the following components:

Start Bit

Signifies the beginning of the data frame.

Data Bits

Typically 5 to 9 bits long, these bits represent the actual data being transmitted.

Parity Bit

Optional. Used for error checking. It can be even, odd, or set to none.

Stop Bits

One or two bits indicating the end of the frame.

Working Principle of USART Frame Format

A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:

  • 1 Start bit
  • 5, 6, 7, 8, or 9 data bits
  • none, even, or odd parity bit
  • 1 or 2 stop bits

A frame starts with the start bit followed by the least significant(LSB) data bit.

Then the next data bits, up to a total of nine, are succeeding, ending with the most significant(MSB) bit.

If enabled, the parity bit is inserted after the data bits, before the stop bits.

When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted.

Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer.

This effectively reduces the number of incoming frames that have to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCM setting but has to be used differently when it is part of a system utilizing the Multi-processor Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address and data frames.

When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU.

This is done by first decoding an address frame to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other Slave MCUs will ignore the received frames until another address frame is received.

Master and Slave MCU Communication Using 9-bit Character Frame Format

For efficient master-slave communication between MCUs, we recommend using a 9-bit character frame format. Here's how it works:

Setting the Master MCU:

  • The Master MCU should be configured to use a 9-bit character frame format (with UCSZ set to 7).
  • During transmission, the ninth bit, TXB8, determines the frame type:
    • An address frame has TXB8 set to 1.
    • A data frame has TXB8 set to 0.

Configuring Slave MCUs:

  • All Slave MCUs should also adopt the 9-bit character frame format.
  • Initially, all Slave MCUs should be in Multi-processor Communication mode, with the MPCM bit in UCSRA activated.

Data Exchange Procedure in Multi-processor Communication Mode:

  1. Every Slave MCU starts in Multi-processor Communication mode (MPCM bit in UCSRA is enabled).
  2. The Master MCU transmits an address frame. Every Slave MCU receives this frame and the RXC Flag in their UCSRA registers becomes active.
  3. On receiving the address frame, each Slave MCU evaluates it via the UDR Register. If the address matches, the MCU deactivates its MPCM bit in UCSRA. If not, it retains its MPCM setting and awaits the next address byte.
  4. The chosen Slave MCU (one with a matching address) will accept all subsequent data frames. MCUs that didn't match the address (and thus have the MPCM bit still set) will disregard these data frames.
  5. Once the final data frame is accepted by the chosen Slave MCU, it reactivates its MPCM bit and prepares to receive a new address frame from the Master. The process then starts over from step 2.

Note on Using 5-bit to 8-bit Character Frame Formats:

While it's feasible to use frame formats ranging from 5-bit to 8-bit, it's not advisable. Switching between n and n+1 character frame formats for the Receiver can complicate full-duplex operations, given that both the Transmitter and Receiver share the same character size setting.

If opting for these smaller frame formats, the Transmitter must be configured to use two stop bits (USBS set to 1). This is because the inaugural stop bit denotes the frame type.

USART Register Description

USART I/O Data Register – UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR.

Bits 7 6 5 4 3 2 1 0
UDR(write) TXB[7:0]
UDR(read) RXB[7:0]

The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB).

USART Control and Status Register A – UCSRA

Bits 7 6 5 4 3 2 1 0
UCSRA RXC TXC UDRE FE DOR PE U2X MPCM

Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data).

If the Receiver is disabled, the receive buffer will be flushed and consequently, the RXC bit will become zero.

Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR).

The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.

Bit 5 – UDRE: USART Data Register Empty

The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written.

Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received (that is, when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA.

Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

Bit 2 – PE: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

Bit 1 – U2X: Double the USART transmission speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting.

USART Control and Status Register B – UCSRB

Bits 7 6 5 4 3 2 1 0
UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8

Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set.

TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set.

UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set.

Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received (that is, when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA.

Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

Bit 2 – PE: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

Bit 1 – U2X: Double the USART transmission speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting.

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